AMD CTO talks Chiplet: The era of photoelectric co-sealing is coming

AMD chip company executives said that future AMD processors may be equipped with domain-specific accelerators, and even some accelerators are created by third parties.

Senior Vice President Sam Naffziger spoke with AMD Chief Technology Officer Mark Papermaster in a video released Wednesday, emphasizing the importance of small chip standardization.

“Domain-specific accelerators, that’s the best way to get the best performance per dollar per watt. Therefore, it is absolutely necessary for progress. You can’t afford to make specific products for each area, so what we can do is have a small chip ecosystem – essentially a library, “Naffziger explained.

He was referring to Universal Chiplet Interconnect Express (UCIe), an open standard for Chiplet communication that has been around since its creation in early 2022. It has won widespread support from major industry players such as AMD, Arm, Intel and Nvidia, as well as many other smaller brands.

Since launching the first generation of Ryzen and Epyc processors in 2017, AMD has been at the forefront of small chip architecture. Since then, House of Zen’s library of small chips has grown to include multiple compute, I/O, and graphics chips, combining and encapsulating them in its consumer and data center processors.

An example of this approach can be found in AMD’s Instinct MI300A APU, which launched in December 2023, Packaged with 13 individual small chips (four I/O chips, six GPU chips, and three CPU chips) and eight HBM3 memory stacks.

Naffziger said that in the future, standards like UCIe could allow small chips built by third parties to find their way into AMD packages. He mentioned silicon photonic interconnect – a technology that could ease bandwidth bottlenecks – as having the potential to bring third-party small chips to AMD products.

Naffziger believes that without low-power chip interconnection, the technology is not feasible.

“The reason you choose optical connectivity is because you want huge bandwidth,” he explains. So you need low energy per bit to achieve that, and a small chip in a package is the way to get the lowest energy interface.” He added that he thinks the shift to co-packaging optics is “coming.”

To that end, several silicon photonics startups are already launching products that can do just that. Ayar Labs, for example, has developed a UCIe compatible photonic chip that has been integrated into a prototype graphics analytics accelerator Intel built last year.

Whether third-party small chips (photonics or other technologies) will find their way into AMD products remains to be seen. As we’ve reported before, standardization is just one of the many challenges that need to be overcome to allow heterogeneous multi-chip chips. We have asked AMD for more information about their small chip strategy and will let you know if we receive any response.

AMD has previously supplied its small chips to rival chipmakers. Intel’s Kaby Lake-G component, introduced in 2017, uses Chipzilla’s 8th-generation core along with AMD’s RX Vega Gpus. The part recently reappeared on Topton’s NAS board.